1. Technical Field
The present invention relates generally to Ball Grid Array (hereinafter xe2x80x9cBGAxe2x80x9d) packages. In particular, the present invention relates to the use of partially captured interconnections, wherein the uncaptured region is selectively oriented in the direction of the highest stress within the BGA package.
2. Related Art
In the manufacture of BGA packages, thermal mismatch between the chip module and the printed circuit board may produce fatigue failure of the BGA interconnections, or solder joints. One solution for this problem is the elongation of the solder joints, which increases the compliance of the solder joints, thereby increasing the fatigue life of the BGA package. Solder joints have been elongated by the use of xe2x80x9ccaptured padsxe2x80x9d which form mask-defined solder joints. Along with increasing the height of the solder joint, the use of captured pads enhances the adhesion of the pads to the underlying chip module or printed circuit board. Unfortunately, stress concentrations within mask-defined solder joints tends to decrease the fatigue life of the solder joints. Alternative techniques employed to elongate the solder joints and increase fatigue life include the use of spacers, high-melt solder columns, selective solder joints containing an excess solder volume, etc. However, many of these techniques reduce the amount of space on the printed circuit board available for wiring.
Accordingly, there exists a need in the industry for a BGA package having an increased fatigue life, without sacrificing wiring space.
The present invention provides an integrated chip package, e.g., a BGA package, having an increased fatigue life, enhanced pad adhesion, while maintaining sufficient wiring space. In particular, the present invention provides a method of forming an integrated chip package having solder joints that are mask-defined in a first direction and pad-defined in a second direction.
The first general aspect of the present invention provides a method of forming an integrated chip package, comprising the steps of: providing a first substrate and a second substrate, each having conductive pads thereon; applying a mask to at least one of the first and second substrates, wherein the mask has a plurality of non-circular openings having a first dimension and a second dimension, such that the conductive pads are not covered by the mask in the direction of the first dimension and partially covered by the mask in the direction of the second dimension; and providing a reflowable material between the conductive pads of the first and second substrates. This aspect allows for an integrated chip package, e.g., a BGA package, having an increased fatigue life, without sacrificing wiring space. It also allows for an integrated chip package having solder joints that are mask-defined in a first direction and pad-defined in a second direction.
The second aspect of the present invention provides an integrated chip package comprising: a first substrate and a second substrate, wherein at least one of the first and second substrates includes a plurality of partially captured pads; and a plurality of interconnections between the first and second substrates. This aspect provides similar advantages as those associated with the first aspect.
The third aspect of the present invention provides a substrate having a plurality of conductive pads and a mask thereon, wherein the mask has a plurality of openings having a first dimension larger than the conductive pad, and a second dimension smaller than the conductive pad. This aspect provides similar advantages as those associated with the first aspect.
The fourth aspect of the present invention provides an integrated circuit mask having a plurality of elongated non-circular openings therein, wherein the openings have a first dimension greater than a second dimension, such that the first dimension of the openings coincides with the direction of the highest stress within integrated circuit. This aspect provides similar advantages as those associated with the first aspect.
The fifth aspect of the present invention provides an integrated circuit interconnection, wherein the interconnection is mask-defined in a first direction and pad-defined in a second direction. This aspect provides similar advantages as those mentioned with respect to the first aspect.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention.